Extraction of Virtual-Source Injection Velocity in sub-100 nm III-V HFETs

We have experimentally extracted the virtual-source electron injection velocity, vx0, of various III-V HFETs at room temperature. This is the carrier velocity that matters for logic applications of these transistors. Sub-100 nm devices with μn > 10,000 cm/V-s exhibit vx0 in excess of 3 × 10 cm/s even at VDD = 0.5 V. This is over 2 times that of state-of-the-art Si devices at VDD > 1. We have verified our extraction methodology for vx0 by building a simple charge-based semiempirical model for the I-V characteristics of III-V HFETs. This model yields an excellent description of the entire I-V characteristics of the devices from subthreshold to inversion and from linear to saturation regimes with fitted electron velocities that are very close to those independently obtained through our proposed extraction methodology. INTRODUCTION The outstanding transport properties of III-V compound semiconductors have fueled interest on these materials for use in the channel material of a future scaled CMOS technology [1, 2]. Certain III-Vs are endowed with very high electron mobilities and peak velocities that result in record values of high frequency responses as indicated by fT and fmax. For logic, however, what matters is the electron injection velocity at the virtual source, vx0 [3]. This quantity is what determines the drain current and the transistor switching speed. To date, there have been very few evaluations of the source injection velocity in III-V FETs [4]. In this work, we carry out a rigorous extraction of the source injection velocity in InGaAs and InAs HFETs with Lg from 130 nm down to 30 nm. The device design and technology used in this work have yielded world-record frequency response [5, 6] which makes these devices ideal for this study. We also show that a simple physical FET model, originally developed for Si MOSFETs, provides an accurate description of the HFET I-V characteristics over its entire regime of operation with source injection velocities consistent with those obtained experimentally. METHODOLOGY The normalized drain current density (ID) in an FET in saturation is given by the product of the areal charge density (Qi_x0) and the velocity (vx0) at the top of the energy barrier in the channel near the source (x = x0) [3]. This is the so-called “virtual source” (Fig. 1). In our approach, Qi_x0 is estimated first, and then vx0 is obtained from vx0 = ID/Qi_x0. Previous efforts to extract vx0 have used simplified models for Qi_x0, such as, for example, a linear dependence of Qi_x0 on VGS above VT [7]. However, in sub-100 nm devices, even a minor error in Qi_x0 results in significant error in the velocity. In our work, we have extracted Qi_x0 by integrating measurements of the intrinsic gate capacitance Cgi at different VGS points in the linear regime. The process is as described next. In particular, we illustrate it on an In0.7Ga0.3As HFET [6].